1. Field of the Invention
The present invention relates to a testing apparatus for a memory IC with a redundancy circuit.
2. Description of the Related Art
Conventional testing apparatuses for a memory IC with a redundancy circuit basically have a structure as shown in FIG. 1. This type of a testing apparatus is disclosed in, for example, Published Examined Japanese Patent Application No. 61-41080. The testing apparatus in FIG. 1 comprises a pattern generator 1 for generating a test pattern, a comparator 3, an address fail memory 4, and a controller 5. An address signal and data output from the pattern generator 1 are supplied to a target memory (memory under test) 2 and data is written at the associated address there. The comparator 3 compares data read out from the target memory 2 with data for the associated address output from the pattern generator 1 to check whether the written data is identical to the read data. The comparison output of the comparator 3 and the address signal from the pattern generator 1 are supplied to the controller 5. Defective information (or failure information) of the target memory 2 is written in the address fail memory 4 under the control of the controller 5. When there exists a defective bit (or failure bit) in the target memory 2, the address fail memory 4, having the same memory space as the target memory 2, is enabled to write the defect information at the associated address.
When a test for all the addresses of the target memory 2 is completed, data stored in the address fail memory 4 is sequentially searched and is read out bit by bit to check the number of defective bits and the associated fail addresses. Based on this defect information, it is determined by means of software whether or not a defect in the target memory 2 can be repaired by the redundancy circuit. If the repairing is possible, memory cells in the row or column where the defect has occurred are replaced with those in the corresponding row or column in the redundancy circuit. When the number of rows or columns where defective bits have occurred is greater than the number of rows or columns of the spare memory cells of the redundancy circuit, it is determined unrepairable.
As described above, the conventional testing apparatuses temporarily fetch defect information, detected during test, into the address fail memory 4, read out data therefrom bit by bit to acquire the number of defective bits and the associated addresses after the test is completed, and determine whether the defective bits can be repaired based on the defect information. It is therefore necessary to search all the addresses in the address fail memory 4 for failed data. The speed for this processing is determined by the processing speed of the hardware of the address fail memory 4. As it is software that determines whether defects can be repaired based on the read-out defect information, the speed for the discrimination processing is determined by the performance of a CPU in use.
Accordingly, the testing performance depends not only on the performance of the hardware of the failure analysis memory (address fail memory), but also on the performance of the CPU, the interrupt processing to the CPU, how to program the CPU, etc., thus making it difficult to improve the processing speed. Particularly, the recent increase in the capacity of target memories considerably reduces processing efficiency to determine whether defective memory cells can be repaired. When many target memories are tested simultaneously to improve the testing efficiency, it is necessary to at last determine whether defective memory cells are repairable for each device, inevitably reducing the multiple-testing originated effects.